With the development of liquid crystal display technology, the integration level of a drive circuit is getting higher and higher, and the volume of an integrated circuit is getting smaller and smaller, which results in degraded anti-static capability of the integrated circuit, for example, in the application of liquid crystal display technology in industrial control area, all signals are subjected to various inferences. As shown in FIG. 1, when gate control signals (including a clock pulse signal (CPV) and an output enable signal (OE)) are interfered, timing skew may occur. Since only when the clock pulse signal and the output enable signal are both at a high level, a gate can be controlled to output, the gate of a thin film transistor cannot be turned, on normally if a timing skew occurs between the clock pulse signal and the output enable signal, thus affecting normal display is of a display device (e.g., defect of ripple occurs).
Therefore, how to avoid timing skew between the clock pulse signal and the output enable signal has become an urgent technical problem to be solved in this filed.